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Disclaimer

All circuits documented here are simulation-only designs — no physical fabrication or silicon verification has been performed. Results are based on Cadence Spectre and NGSpice simulations using real foundry BSIM4 PTM 65nm models.

These documents are shared for portfolio and demonstration purposes only and are not intended as educational or reference material. Use in any production or critical application without independent verification is strongly discouraged.

The documentation is Licensed under CC BY 4.0, while the QUCS-S Schematics are Licensed under MIT License. Read the LICENSE.txt in each of these repositories for more information.

Parasitic Vertical BJT Parameter Summary

PNP Diodes

Process: Custom 65nm CMOS  ·  Supply: VDD = 1.2 V  ·  Lmin = 65 nm

PNP 20 X 20

Parameter Value Comments
Emitter Area 2x2 µm2 Geometry info
η 1003.6 m Forward current emission coefficient for Emitter-Base junction (SPICE Model parameter, NF)
IS 0.285 aA Saturation Current
VBE
  • 0.777 V
  • 0.723 V
  • 1 Diode
  • 8 Diodes in parallel
(At a current of 5 µA)
\(dV_{D}/dT\)
  • -1.55 mV/°C
  • -1.75 mV/°C
 Change in the diode’s voltage with temperature for:
  • 1 Diode
  • 8 Diodes in parallel
(At current of 5 µA)