Disclaimer

All circuits documented here are simulation-only designs — no physical fabrication or silicon verification has been performed. Results are based on Cadence Spectre and NGSpice simulations using real foundry BSIM4 PTM 65nm models.

These documents are shared for portfolio and demonstration purposes only and are not intended as educational or reference material. Use in any production or critical application without independent verification is strongly discouraged.

The documentation is Licensed under CC BY 4.0, while the QUCS-S Schematics are Licensed under MIT License. Read the LICENSE.txt in each of these repositories for more information.

Current Starved Ring VCO (CS-VCO)

Prerequisites

The procedure for fixing the range resistor value uses the substitution theorem, which is covered extensively in the Beta Multiplier Reference (BMR). Specifically, refer to the Fixing Resistor Value section there before proceeding — the rationale and testbench methodology described there apply directly here.

Introduction

I have documented only the design procedure, and anything relevant to that. For theory of operation, please refer to standard textbooks or any lectures.

Before we proceed, let's take a look at the schematic of CS-VCO.

Figure-01: CS-VCO schematic diagram [Ref. CMOS Circuit Design, Layout and Simulation, Fig 19.25]

Such a VCO will posses a low-gain and a linear transfer curve as shown in Figure-02.

Figure-02: Transfer curve of CS-VCO of Figure-01 [Ref. CMOS Circuit Design, Layout and Simulation, Fig 19.26]

For use in XOR DPLL

The schematic diagram of CS-VCO shown Figure-01 is a modified variant to posses low gain and linear transfer function. This modified CS-VCO is suitable for use in an XOR DPLL.

The reasoning behind these modifications and the motivation for choosing a low gain and linear transfer function are not discussed here. As before, for a detailed explanation of how this circuit works, you can refer to standard textbooks or lecture materials.

Design Considerations

For this documentation, the center frequency is taken to be 500 MHz, that is f_out = 500 MHz when V_in,VCO = V_DD/2 = 0.6 V.

And to design this, we need to chose values for four things:

• MOSFET Sizes (for both NMOS and PMOS) suitable for Current starved inverter
• Input NMOS size (VCCS MOSFET)
• Lower limit resistor value
• Range resistor value

The MOSFET sizes suitable for digital design are already chosen, and their parameters are thoroughly listed in Switching Parameters (Chosen Size) section of Digital Models table. For the sake of convenience, sizes are listed here:

Flavour	W/L (Drawn)	W/L (Actual)	Rn,p	Coxn,p
NMOS	10/1	650 nm / 65 nm	3.4 kΩ	561 aF
PMOS	20/1	1.3 µm / 65 nm	3.4 kΩ	1.06 fF

Table-01: Sizes and Parameter summary

This leaves us with the remaining three: Input NMOS size, Range resistor value, and Lower limit resistor value, but before we address them, let's estimate the current used in Current-starved inverters for operating frequency of 500 MHz.

Estimating minimum current in Current starved inverter

CS-VCO ouput frequency is related to current through Equation-01.

\[\tag{1} F_{osc} = \frac{I_D}{N * C_{tot} * V_{DD}}\]

where,

• C_tot is total capacitance at output of current starved inverter.
• N is the number of stages.

---

C_tot is estimated from Figure-03:

Figure-03: Capacitance loading each current starved inverter [Ref. CMOS Circuit Design, Layout and Simulation, Fig 19.15]

And is given by,

\[C_{tot} = C_{in} + C_{out} = (C_{ox,n} + C_{ox,p}) + \frac{3}{2} (C_{ox,n} + C_{ox,p}) = \frac{5}{2} (C_{ox,n} + C_{ox,p})\]

From Table-01, we get C_oxn,p as 561 aF and 1.06 fF for the chosen sizes.

Therefore,

\[\tag{2} C_{tot} = \frac{5}{2} (561 ~aF + 1.06 ~fF) = 4.052 ~fF\]

---

It is generally recommended to keep a minimum of 5 stages, i.e., \(N \ge 5\)

Using this in Equation-01 yields,

\[N = \frac{I_D}{f_{osc} * C_{tot} * V_{DD}} \ge 5\]

We know our target frequency is 500 MHz, and the V_DD is 1.2 V.

\[\frac{I_D}{500 ~M * 4.052 ~fF * 1.2 ~V} \ge 5\]

\[I_D \ge 12.16 ~\mu A\]

It is always good to leave some margin from minimum values. So, our target current is taken to be 20 µA (> 12.16 µA).

\[I_{D,target} = 20 \mu A\]

Sizing the input VCCS NMOS

The input NMOS along with degeneration resistor acts as a linear VCCS. The difference between input voltage and V_GS developed is dropped across the resistor to generate an output current.

\[I_{out} = \frac{V_{in,VCO} - V_{GS}}{R_{range}}\]

Clearly, for different values of current, different V_GS develops and that leads to a non-linear output current. We don't want that.

Ideally, we want the V_GS generated to be constant regardless of the output current.

Fixing non-linear V_GS with a wide MOSFET

The solution to this problem is to make this input NMOS really wide. Calling a MOSFET wide depends on the context of the current it can conduct. For example, sizing a MOSFET to conduct 50 µA and then actually make it conduct 5 µA makes it wider for the use case.

Under such conditions, the V_GS developed will be lower than what it generates to conduct it's target current. When this is so, for all the range of output currents which gets developed, a wide MOSFET need not to turn ON harder.

In fact, if we make it ridiculously wide, it will barely turn ON and develop a \(V_{GS} \approx V_{TH}\) and will remain the same as long as the current that actually flows is too smaller than what it is sized to conduct.

This makes us to define our target current range, so we can size an NMOS that can be considered wider with respect to these current range.

Target current range for input VCCS

We will target a current range of 2 µA, with the actual currents varying from 0 A to 2 µA.

I found this value while playing around with the input current to a CS-VCO. In fact, in later parts of this documentation, we will find that this estimate is good enough.

Follow along, you will find that this value is a good starting point.

This particular value of 2 µA seems overly arbitrary, and the explanation given feels a bit vague?

I understand that this feels like I am randomly throwing a number out of the blue. This feeling is valid. But,

An actual design doesn't follow a linear procedure. You calculate a value for something and proceed to the next step only to find an error which makes you to trace back 10 steps, essentially re designing it.

So explaining such a non-linear journey in a linear story format is extremely difficult and one of the major reasons why textbooks are often confusing until you try to build what it says.

The only way to know what value will be enough is to experiment with a bunch of values.

I started with a range of 5 µA and found it to posses too much gain, and then reduced it to 2 µA. You iterate. You iterate a lot and see failures. Only then, will you able to say that this much is enough. In short, gain experience.

In order to back this statement, see the refined procedure below which I became capable of giving, only after fully designing it.

Refined procedure to find a value for this range current

This is not the way the documentation follows, but is the refined procedure developed through experience. The documentation follows the actual journey I took in designing this, but this refinement is something I concocted after completing the design of CS-VCO.

Now, much of the design in CS-VCO of Figure-01 revolves around the input VCCS.

And you need a range of current to even start designing the said VCCS. So, using Substitution theorem, why not just replace the entire current generator portion with an ideal current source to conduct some abstract simulations to find a reasonable estimate?

Figure-04: Testbench to figure out the input current range

With this substitution highlighted in Figure-04, step through various current values for the ideal current source to generate the transfer curve as shown in Figure-28.

And in order to do that, you need to know how many stages is needed to construct an abstract CS-VCO. For this, you know that you have taken a current of 20 µA from Estimating minimum current section. But from the discussion on Finding actual current in Current Starved Inverter section you will come to know that the current in the inverter will not be exactly 20 µA.

So, you will set to out find the actual current in inverter, by using the testbench illustrated in Figure-22. And then you will follow the discussion on Computing the number of stages section to get the value for N.

And then, you generate Figure-28 from which you will come to know, how much sensitive your CS-VCO is, and then define a suitable constraint on the input current range.

Again, the constraint gets defined by the requirements for the VCO by the overall system. In my case, this is being built for use in an XOR DPLL, which itself paints a constraint on centre frequency of 500 MHz, and an output range of no more than 10 MHz around this frequency.

And then you choose a current range with the above discussions and you try designing it. See the result. Is it satisfactory? Good. If not, just re-iterate.

---

Feeling confused? I understand this jumbled instruction is confusing. Why not revisit this section after you complete this documentation? I am sure, that you will understand that this is the refined way to design this, after you finish this documentation.

Sizing a wide NMOS

With all the previous discussions, the maximum current this NMOS will conduct is just 2 µA. And because it is so wide, it will just develop a V_GS of V_TH.

In order to size this NMOS, all we have to do is:

• Fix \(V_{GS} = V_{TH} = 430 ~mV\). (V_TH comes from Regular Threshold Voltage (RVT) table)
• And then choose a size which shows an I_D vs V_DS curve with current values slightly larger than 2 µA (say 5 µA or even 6 µA) to leave some margin.

Following this, I have chosen a size of 66.2/1 and it's I_D vs V_DS curve for a V_GS of 430 mV is shown in Figure-05.

Figure-05: I_D vs V_DS curve of a 66.2/1 NMOS with a V_GS of 430 mV \(\approx V_{TH}\)

How come 66.2/1 (4.3 µm/65 nm) is considered wide?

A 66.2/1 (4.3 µm/65 nm) may not seem ridiculously wide, but don't be fooled by the width being 4.3 µm. Look at Figure-05. This NMOS can conduct a current of 5 µA while having a V_GS of just the threshold voltage and a V_DS of 200 mV!

Normally, when you see the I_D vs V_DS curve for any MOSFET which is barely ON (or with a \(V_{GS} \approx V_{TH}\)), it will have at most a couple of µA. Meanwhile Figure-05 shows a current of 5 µA with just a V_DS of 200 mV while barely turning ON! And it even goes up to several tens of µA!

This is possible only when your MOSFET is ridiculously wide!

Still not convinced with this? How about increasing the length to 2? With a drawn length of 2 (or actual length of 130 nm), you get a width of 116.9 (7.6 µm) to conduct a similar current of 5 µA at about a similar V_DS of 200 mV!

An NMOS with a width of 116.9 is simply too ridiculous considering that the negative charges in the channel are more mobile than the one in PMOS, and this size would have pulled ridiculous amounts of current if the V_GS were to increase above threshold. See Figure-06 which shows the I_D vs V_DS curve with a V_GS of 430 mV.

Figure-06: I_D vs V_DS curve of a 116.9/2 NMOS with a V_GS of 430 mV \(\approx V_{TH}\)

Another way to accept that this is a wide NMOS is to see the aspect ratio and not the actual dimensions. A 66.2/1 size is too large for use in digital design considering such wider MOSFETs tends to load your previous stage.

With this chosen, let's address the lower limit resistor

Why do you need this lower limit resistor, R_low?

A quick glance at Figure-01 can puzzle you as to why we attach the resistor R_low. Addressing this is really important, because once we understand it's role, we can then replace it with a MOSFET for ease of integration.

Recall that an XOR DPLL needs a VCO with low gain, and whose TF curve is centered around a frequency f_center as seen in Figure-02.

That is, even when input voltage were to go to ground, the output frequency shouldn't go below a lower limit in order for the XOR DPLL to not lose lock or worse, lock onto harmonics of center frequency.

With that said, think about what happens without this resistor? If this resistor was not present, then all you have is just the source degenerated NMOS. And when the input voltage goes down, so does the current (As an NMOS needs some V_GS to conduct a current)! And with that your output frequency will also go down without settling to a lower limit!

So, you get a Transfer curve as seen in Figure-07 where the output frequency just continues to go to lower frequencies as your input voltage goes down.

Figure-07: Transfer Curve of a CS-VCO without lower limit resistor [Ref. CMOS Circuit Design, Layout and Simulation, Fig 19.18]

So, it's important to establish a lower limit on the output frequency in some way, ensuring that even when the input voltage drops and turns our input NMOS off, the VCO will still continue to oscillate at its lowest possible frequency.

Fixing a lower limit to output frequency by adding a constant current to Input Controlled Current

The solution to the lower limit problem is concocted from the observation that VCCS MOSFET shuts off as input voltage goes low and Output current also goes low. So,

What if we add a dummy constant current along with the input controlled current? Like a current source in parallel with MOSFET?

Like the one shown below:

Figure-08: A dummy current load which always pulls a current regardless of input MOSFET ON/OFF state

When this is done, even if I_VCCS where to vanish, thanks to current source pulling a non-zero current at all times, the VCO's output frequency will now have a lower limit!

Implementing this current source - Simple resistor as a pull down load

If the VCCS is off, that is V_in,VCO is so low, then, you have only the current source as a pull down. So, in that case, consider this modification:

Figure-09: MOSFET resistor bias leg to derive a non-zero current

The benefit of this modification is it sets a lower frequency limit (i.e. a lower current limit) regardless of input voltage and so, the TF seems to get an offset.

Figure-10: A lower limit in TF curve manifesting as an offset due to dummy load current

Success

And this is desirable, as the VCO cannot wander to lower frequencies thanks to the lower limit. Thus, the addition of resistor limits the lower frequency by sinking a non-zero current even if VCCS MOSFET turns off.

Any possible issue with supply dependance?

Of course, Diode Connected PMOS and Resistor together forms a voltage divider, which heavily depends on supply. But, That is not a concern as the PLL is an extremely sensitive circuit and generally, such circuit blocks gets accompanied by Supply regulators (LDO).

Not Convinced with the above reason?

Imagine, even if we make the current source somehow independent of supply voltage, because we're using the ring oscillator topology, the frequency of oscillation is still dictated by supply voltage! (see Equation-01)

I mean think about it, Ring oscillator is just a bunch of inverters (in odd number of quantity, very important) connected in a loop. If supply drops down, then the inverter output voltage range also drops down, thereby making it easier to cover this reduced range in little time (i.e. frequency has changed).

There's no point in making a supply independent current source, when the VCO itself has so much supply dependance. Let's just push it onto the regulator from a system perspective and relax!

A MOSFET only solution

If we have opted to use a simple MOSFET resistor divider, we can also opt for MOSFET only dividers as shown in Figure-11.

Figure-11: Replacing resistor with an NMOS as pull-down

The Pull-up PMOS has the standard digital size as characterized in Table-01 and the pull-down NMOS can be sized easily noting that our target current is 20 µA (see Estimating minimum current in Current starved inverter section).

With this in mind, I have sized the pull-down NMOS to be 66.2/10 (4.3 µm/ 650 nm) in order to roughly pull a current of 20 µA as seen in Figure-12.

Figure-12 Sizing the pull-down NMOS [66.2/10 (4.3 µm/ 650 nm)] for a current of 20 µA

Fixing the range resistor, R_range

We've already chosen a range current of 2 µA (see, Target current range for input VCCS section), and the sizes for input NMOS (66.2/1) and lower limit NMOS (66.2/10).

It is time to choose the range resistor value. The trick in finding this resistor lies in our TF curve. Since our supply voltage is 1.2 V, an acceptable range of input voltages, V_in,VCO can be from 0.4 V to 1.0 V. There is no way a VCO can accommodate full supply rail as it's input voltage range, as near the rails, our TF can show severe non-linearity (more on this later).

Concocting a tesbench to find this resistor

Just as stated in the Prerequisites section, we will invoke the Substitution theorem, but with a little modification. This is not exactly the substitution theorem, rather something inspired by it.

Remember, that we need our output current to have a range of 2 µA, that is, 0 A to 2 µA when V_in,VCO varies from 0.4 V to 1.0 V.

Info

Input voltage range may extend past 0.4 V to 1.0 V range, and this is taken arbitrarily.

Therefore,

• when V_in,VCO takes it's maximum value of 1.0 V, the output current should be 2 µA.
• And this current must linearly vary with input voltage with the slope dictated by the maximum limit, in it's input voltage range.

This is easily achieved by substituting an Ideal VCCS with a transfer ratio of:

\[Transconductance ~of ~VCCS, ~A_{VCCS} = \frac{2 ~\mu A}{1 ~V} = 2 ~\mu S\]

in place of our range resistor as seen in Figure-13.

Figure-13: Substituting the range resistor, R_range with an ideal VCCS of transfer, A_VCCS of 2 µS

Such a substitution allows us to see how the total current varies even before we fix our resistor value. Let's see this variation by sweeping the input voltage, V_in,VCO.

Current Variation with input Voltage

The results of sweeping the input voltage are shown in Figure-14.

Figure-18: Input Voltage sweep Vs (a) Range Current, (b) Voltage developed across VCCS and (c) Total Current

Some observations:

• The linear range current and it's value at V_in,VCO of 1.0 V as 2 µA is unsurprising, considering an ideal VCCS is used.
• The voltage developed across VCCS goes negative roughly below an input voltage, V_in,VCO of 0.3 V as seen from Figure-18(b). It also saturates above 1.0 V, indicating our potential range of input is 0.3 V to 1.0 V
• Total current variation is just 1 µA instead of 2 µA as seen from Figure-18(c).
  This is easily explained from the fact that the diode connected lower limit NMOS reduces the pull-down current if the voltage across it reduces, which it does, when the input VCCS pulls additional current through pull-up PMOS, essentially increasing the voltage drop across it.

In fact, this is good for us, as lesser the variation in input current, the lesser the gain of CS-VCO.

Computing the value of this resistor

Following Fixing Resistor Value section of Beta Multiplier Reference (BMR), we have found the voltage across ideal VCCS at maximum current of 2 µA to be 537.89 mV from Figure-18(b).

Therefore,

\[Range ~resistor, R_{range} = \frac{537.89m}{2 \mu} = 268.9 ~k\Omega \approx 270 k\Omega\]

This is a huge resistance, but it is necessary to ensure low gain. We will see that this value is justified shortly in Transfer function measurement sections.

Current Generator summary

Much of the design is complete, as the current generator is the elephant in the room. Let's summarize the results here for convenience:

Instance	Value	Comment
Input VCCS NMOS	66.2/1	Actual Dimensions: (4.3 µm / 65 nm)
Lower Limit NMOS	66.2/10	Actual Dimensions: (4.3 µm / 650 nm)
Rrange	270 kΩ	For low Gain

Table-02: Current Generator instance values summary

And the complete schematic of current generator is shown in Figure-19.

Figure-19: Final schematic of Voltage controlled Current generator portion

Let's see how this performs. The currents generated when input voltage is swept are shown in Figure-20.

Figure-20: Input Voltage sweep Vs (a) Range Current and (b) Total Current for R_range of 270k (Figure-19)

The output currents are very linear, with the total current having a lower limit close to 20.05 µA as seen in Figure-20(b). The range current is 2 µA as we designed it, and the variations in total current is 1 µA just as explained in Current Variation with input Voltage section.

Again, from Figure-20, our acceptable input voltage range is from 0.3 V to 1.0 V just as explained in Current Variation with input Voltage section.

Notice how 0.6 V is present in the linear portion of the curve. This is really important as we want V_DD/2 (0.6 V) to be in the linear operating region and not in the non-linear region as XOR Phase detector average output in locked state is V_DD/2.

Fixing the number of stages for Ring Oscillator

Now that our current generator design is complete, it's about time we found the number of stages needed for a center frequency of 500 MHz. Even though our target current is 20 µA for center frequency, it would be better if we found the actual current in the current starved inverter to reduce the errors in our hand calculations.

The current starved inverter schematic is shown in Figure-21.

Figure-21: Current Starved Inverter cell schematic (Sizes from Table-01)

Clearly, from Figure-21 the current in the inverter cell is controlled by VBP and VBN voltages which are generated using the principle of current mirror. And this is exactly why, instead of using 20 µA, we will find the actual current in the inverter using simulations to account for errors in current mirror.

Finding actual current in Current Starved Inverter

To that end, see the testbench for finding current in inverter shown below.

Figure-22: DC Annotated testbench to find current in inverter (Sizes from Table-01 and Table-02) (V_in,VCO = 0.6 V to find center current)

This is nothing but a partial schematic of Figure-01.

Some commentary:

• Input voltage is 0.6 V, as Equation-01 is used with center frequency and current used for center frequency. And for XOR DPLL, VCO TF is chosen to have the center frequency at V_DD/2 (0.6 V) as XOR Phase detector average output in locked state is V_DD/2.
• Notice how the Inverter's pull-up and pull-down paths are turned ON by appropriately giving GND and V_DD to PM3 and NM4. This is important as only when we do this, we allow a current to flow in the inverter, which is needed to compute the number of stages.
• Also, the output of inverter is forced to V_DD/2 (0.6 V) by an ideal voltage source. This is also important, as this let's us to estimate the average current in the inverter by creating a symmetric operating condition.
• Clearly, the generated current is 20.54 µA (PM1) and the final current in the inverter is 17.79 µA (PM2) and 17.51 µA (NM3).

This is exactly what we need.
The pull-up current is 17.79 µA while the pull-down current is 17.51 µA.

So, the final current in the inverter is just the average of these two:

\[\tag{3} Average ~Current ~in ~inverter, I_{D,avg} = \frac{17.79 \mu + 17.51 \mu}{2} = 17.65 ~\mu A\]

Computing the number of stages, N

From Equation-01, we can write,

\[N = \frac{I_{D,avg}}{f_{osc} * C_{tot} * V_{DD}}\]

where, I_D,avg is 17.65 µA (Equation-03), f_osc is 500 MHz, C_tot is 4.052 fF (Equation-02) and V_DD is 1.2 V.

Therefore,

\[N = \frac{17.65 \mu}{500M * 4.052f * 1.2} = \lfloor 7.26 \rfloor = 7\]

So, the number of stages in the CS-VCO is 7.

Note

We need 7.26 stages to have an output frequency close to 500 MHz, but 0.26 stage doesn't make any sense and hence we floored it's value to nearest odd number, being 7.

What this means? We may need to iterate to bring 500 MHz into our range of output frequencies.

TRANSIENT Simulations

The schematic of CS-VCO with 7 stages of current starved ring topology is shown in Figure-23.

Figure-23: CS-VCO schematic with 7 stages (Sizes from Table-01 and Table-02, Current starved Inverters from Figure-21)

Notice how two normal inverters (sizes from Table-01) are attached between the actual output and the output of ring oscillator. This will make sure to clean the output waveform into nice square waves.

From our previous discussions, the number of stages being 7 may put us slightly away from 500 MHz, making it necessary to iterate.

Iteration 1 - Using calculated values

The testbench for measuring Transfer function for CS-VCO of Figure-23 is shown in Figure-24.

Figure-24: Testbench to plot transfer function of CS-VCO of Figure-23

Now all we have to do is to step through the input voltage from 0.4 V to 1.0 V in steps of 0.05 V and then measure of output frequency of resulting waveforms.

The transfer function generated in this way is shown in Figure-25.

Figure-25: Transfer function of CS-VCO of Figure-23

Some observations:

• Just as we speculated, our output tuning range doesn't include our target frequency of 500 MHz.
• The achieved center frequency is 510.74 MHz.
• Our upper limit seems to be 0.95 V as beyond that, our curve seems to bend a little.
• Our TF is very linear with an output tuning range of 505.5 MHz to 521.5 MHz, 16 MHz range.

We need to somehow shift this curve to lower range to include our target frequency of 500 MHz.

Let's iterate.

Iteration 2 - Adjusting lower limit NMOS

Clearly, from the discussion on Fixing the lower limit section, we see that the knob that adjusts the output frequency lower limit to include 500 MHz is the lower limit NMOS.

This was clearly explained in Figure-10. [Meanwhile, the range is still set by our input VCCS NMOS along with degeneration resistor R_range. And from Iteration 1, it resulted in a range of 16 MHz.]

But the question is, by how much should you adjust this lower limit NMOS?

We are aware, that the input current sets the output frequency. Right now, it is voltage controlled.

Tip

What if we completely substituted it with an ideal current source and stepped through several values around 20 µA to find a suitable value?

This is far better than mindlessly sizing the lower limit NMOS.

To that end, the input current generator portion is completely removed to allow attaching of a current source as shown in Figure-26.

Figure-26: Modifying the current generator portion to allow direct connection to an ideal current source

And then, the testbench directly inputs a current instead of a voltage source to the VCO Cell of Figure-23, as shown in Figure-27.

Figure-27: Testbench to generate TF curve Vs I_in,VCO (Input current)

Let's step the current source around 20 µA. Let's step from 18 µA to 21 µA in steps of 0.5 µA to get a TF Curve Vs I_in,VCO.

The results of such a simulation is seen in Figure-28.

Figure-28: Transfer function of CS-VCO of Figure-23 for current input

---

Clearly, a change of 0.5 µA in input current yields a change of roughly 10 MHz in it's output frequency. And we know from Iteration 1, the range of output frequencies is 16 MHz.

So, if we want to include 500 MHz near the center frequency, we can't afford to reduce current by 0.5 µA, as that will bring the frequency down by 10 MHz as the range is just 16 MHz.

Confused as to why reducing by 0.5 µA is bad?

Think about it, if I reduced the lower limit current by 0.5 µA, then, from Figure-28, the new lower limit is 489 MHz. And with a range of 16 MHz, the output frequencies will vary from 489.8 MHz to 505.8 MHz, which puts 500 MHz close to upper limit, making the XOR DPLL difficult to lock onto it.

Recall that the XOR Phase Detector has an average output of V_DD/2 (0.6 V) when the PLL has obtained lock. And this mandates that our target 500 MHz be mapped to an input voltage near V_DD/2.

So, our only option is to reduce Lower limit current by 0.25 µA. I know this is ridiculous, but it is what we can do right now.

Note

This also highlights how difficult it is to set a desired output frequency as the center frequency in a practical CS-VCO. It is really hard to do this when we fabricate.

New lower limit and TF curve

Following the above discussion, I have adjusted the size of lower limit NMOS to 63.1/10 (4.1 µm/ 650 nm). And the resulting current can be seen in the DC annotated schematic of Figure-29.

Figure-29: New lower limit current for adjusted pull-down NMOS of 63.1/10 (4.1 µm/ 650 nm)

Warning

Notice that I haven't precisely made the current to be 0.25 µA less than 20 µA. This is a futile thing to do, considering that the MOSFET may suffer from process variations. So, some rough value should be fine.

Changing the lower limit NMOS of Figure-23 with 63.1/10 (4.1 µm/ 650 nm), and then using the testbench of Figure-24 yields the transfer curve of Figure-30.

Figure-30: Transfer function of CS-VCO of Figure-23 with lower limit NMOS size adjusted to 63.1/10 (4.1 µm/ 650 nm)

The new transfer function has a center frequency that is close to 500 MHz. This is satisfactory and we will stop the iteration here.

The obtained output frequency range is 495.5 MHz to 512 MHz over an input voltage range of 0.4 V to 1.0 V.

The gain of this VCO is,

\[Gain ~of ~CSVCO, A_{CSVCO} = 2\pi * \frac{512M - 495.5M}{1 - 0.4}\]

\[A_{CSVCO} = 2\pi * 27.5 ~MHz/V = 172.79 ~Mrad/sV\]

Sample output waveform

For completeness sake, let's look at a sample output waveform for V_in,VCO = 0.6 V (V_DD/2) shown in Figure-31.

Figure-31: Output waveform for input voltage of 0.6 V (V_DD/2)

The waveform looks clean, thanks to the normal inverters attached to the output.

Let's make a rough estimate for output frequency from Figure-31 and cross-verify it with Figure-30. The waveform in Figure-31 has markers attached to rough points marking one cycle, suitable to make an estimate for output frequency.

\[f_{out} = \frac{1}{18.755 ~ns - 16.759 ~ns} = \frac{1}{1.996 ~ns} = 501 ~MHz\]

Looking at Figure-30, we know that this f_out is close to 500.94 MHz. Such errors are inevitable considering we eyeballed our time points for a rough estimate, which once again asserts the accuracy of measurement function implemented in SPICE (SPECTRE), and why you should use that to generate the TF curve.

Conclusion

The design of CS-VCO is complete. The final design choices are summarized in Table-03.

Instance	Value	Comment
Input VCCS NMOS	66.2/1	Actual Dimensions: (4.3 µm / 65 nm)
Lower Limit NMOS	63.1/10	Actual Dimensions: (4.1 µm / 650 nm)
Rrange	270 kΩ	For low Gain

Table-03: Current Generator instance values final summary

And the parameters of CS-VCO are summarized in Table-04

Parameter	Value	Comments
ACSVCO	172.79 Mrad/sV	or 27.5 MHz/V
fcenter	500.94 MHz	For Vin,VCO = VDD/2 = 0.6 V
fout,range	16.5 MHz	From 495.5 MHz to 512 MHz
Vin,VCO,range	0.55 V	From 0.4 V to 0.95 V

Table-04: CS-VCO Parameter summary

QUCS-S / NGSPICE simulations

This circuit is also built and tested in QUCS-S / NGSPICE and the simulation results are available in this document.

Note

• QUCS-S/NGSPICE doc uses slightly different sizes for simulation. It is also correct and yields a center frequency of 511 MHz. Unlike the design here, it didn't received another iteration to include 500 MHz in it's output tuning range.
• The gain is also higher than this design: 215.41 Mrad/sV (or 34.283 MHz/V) due to R_range being 216 kΩ. The output range is from 504.8 MHz to 525.3 MHz. This is too much gain and range for an XOR DPLL, but nevertheless, since it is a functional design, it is mentioned here, with the associated remarks regarding this design noted in this comment.