Disclaimer

All circuits documented here are simulation-only designs — no physical fabrication or silicon verification has been performed. Results are based on Cadence Spectre and NGSpice simulations using real foundry BSIM4 PTM 65nm models.

These documents are shared for portfolio and demonstration purposes only and are not intended as educational or reference material. Use in any production or critical application without independent verification is strongly discouraged.

The documentation is Licensed under CC BY 4.0, while the QUCS-S Schematics are Licensed under MIT License. Read the LICENSE.txt in each of these repositories for more information.

Series Realized Band Gap Reference (BGR)

Prerequisites

This design shares methodology with the Beta Multiplier Reference (BMR). The following sections are directly applicable here and are not repeated:

• Fixing Resistor Value — procedure to find resistor value using the substitution theorem
• Startup Circuit Design — design considerations and procedure are identical to the BMR.
• Using MOSFET as a capacitor to compensate the feedback loop — NMOS capacitor vs PMOS capacitor and it's effects on startup

Read those sections before proceeding.

Introduction

I have documented only the design procedure, and anything relevant to that. For theory of operation, please refer to standard textbooks or any lectures.

Before we proceed, let's take a look at the schematic of Series BGR.

Figure-01: Series BGR Schematic Diagram (Startup not shown)

The PNP BJTs are vertical parasitic components that can be used to generate a V_BE voltage (CTAT) in a CMOS process. One such diode is characterized in PNP 20 X 20. The parameters listed there are what we will use to design the BGR, and as such, some necessary parameters for our design are summarised in Table-01:

Parameter	Value	Comments
η	1003.6 m	Forward current emission coefficient (Emitter-Base junction)
VBE	0.777 V	1 Diode (At a current of 5 µA)
\(\delta V_{BE}/\delta T\)	-1.75 mV/°C	Change in the diode’s voltage with temperature (at current of 5 µA) for 8 Diodes in parallel

Table-01: PNP Diode summary

Why 8 PNP Diodes in parallel? Why the number 8?

This is entirely due to the ΔVBE caused by the emitter area mismatch between a single PNP diode and K PNP diodes connected in parallel (with both having same current), where K is any integer.

\[\Delta V_{BE} = \eta V_{T} \ln K\]

From PNP 20 X 20, we see that η = 1003.6m and V_T = 26 mV (at room temperature). Plugging it into the above equation yields:

\[\tag{1} \Delta V_{BE} = 1003.6m * 26m * \ln 8 = 54 mV\]

Just 54 mV! For 8 PNP Diodes in parallel. Some people will even go for a K of 100, to get a ΔVBE of 120 mV. I know it is painful, but see that to double what we got before with just 8 diodes, now needs 100 diodes. Logarithmic functions are scary!

Quote

Because the logarithm function compresses its argument... if the argument is increased by a factor of ten, ΔVBE increases by only \(V_{T} * \ln 10 \approx 60 mV, ~\eta \approx 1\).

- Ref. Analysis and design of Analog Integrated Circuits: Gray, Meyer, Hurst, Pg 324

That is why, I choose 8. Keeping 10 diodes is also a good choice (for a ΔVBE of 60 mV), but I am going to stick with 8.

For designing this, we need to find:

• a Size for current sourcing PMOS.
• Value of PTAT Current generator resistor, R₁.
• Error amplifier topology plus sizes for MOSFETs used to build it.
• Value of PTAT voltage source resistor, R₂.

The MOSFET sizes are already choosen and their parameters are thoroughly listed in I/O Device — 500 nm table. Unless specified otherwise, these sizes will be the ones we use to construct the entire circuit.

And as such, these are tabulated here for convenience:

Flavour	W/L (Drawn)	W/L (Actual)	ID	VGS
NMOS	5.8 / 1	2.9 µm / 500 nm	10 µA	740 mV
PMOS	13.8 / 1	6.9 µm / 500 nm	10 µA	690 mV

Table-02: Sizes and Bias Current summary

Question

The observant reader would have questioned these sizing choices considering Table-01 characterizes PNP Diodes for 5 µA while here it is characterized for 10 µA. But still, follow along. These sizes are chosen for a general analog design. Just to tease you on how these two gets tied up, the error-amp steps in to adjust the V_SG of top PMOS in Figure-01 to reduce it's current to 5 µA.

This leaves us with values for resistors R₁ and R₂ and the error amplifer.

Fixing PTAT Current Generator resistor, R₁

Prerequisites section has already listed the knowledge needed to choose a suitable value for this resistor. Review the listed sections to grasp the reasoning behind the testbench employed to determine the value of resistor, R₁.

The amplifier and the feedback loop will:

1. Force the same voltage across the single diode on the left as well as the resistor R₁ and eight diodes on the right.
2. Both of these branches will conduct 5 µA.

Using Substitution theorem, the testbench is built and can be seen in Figure-02.

Figure-02: PTAT Current Generator resistor R₁ value Testbench

Notice how we got 54.3 mV, which is very close to what is predicted by Equation-01.

And so, with this voltage, to set a current of 5 µA, we need a resistor of:

\[R_{1} = \frac{\Delta V_{BE}}{I} = \frac{54.3m}{5\mu} = 10.86 k\Omega \approx 10.9 k\Omega\]

Now all we need is the error amplifier.

Added error amplifier

We need to pick a topology for the error amplifier. Let's go for a single stage diff-amp because:

• It will have sufficient gain (Given L_min of I/O MOSFET is 500nm. See Table-02)
• It will be easy to compensate.

Tip

Always start with the simplest topology possible. If it proves insufficient, you can always add another stage or modify it.

NMOS input or PMOS input ?

Constraint on output common mode

At steady state, both inputs of error-amp will settle to same voltage due to negative feedback loop (or close to each other based on DC Gain). And so, with just a common-mode voltage, the error-amp is expected to set bias voltage for Current sourcing PMOS in Figure-01.

And looking at Table-02, we find that the V_SG of PMOS for the chosen size is 690 mV to source 10 µA. Our design has chosen 5 µA, and so the V_SG needed will be slightly lower than 690 mV for the same size.

But nevertheless, using this value, the steady voltage at gate of PMOS needed for this V_SG is given by

\[\tag{Rough estimate} V_{G,P} = V_{DD} - V_{SG,P} = 3.3 V - 0.69 V = 2.61 V\]

And 2.61 V is close to V_DD of 3.3 V for 10 µA. And it will be even closer for 5 µA as V_SG would have reduced for the same size.

So, the observation from here is:

Constraints on Error amplifier output common mode

Our amplifier output common mode should be close to V_DD.

Figure-03: Output Common Mode of NMOS and PMOS input diff-amp

From Figure-03, we could be inclined to think it's an NMOS input differential amplifier, but let's not jump to conclusions yet—there's still another issue to consider.

Inherent constraint on Input common mode of NMOS and PMOS Diff-amp

What exactly is the common mode voltage we expect to see? Looking at Table-01, we see that V_BE is 0.777 V for a current of 5 µA (single diode). And this is the value generated at left side single diode which is also copied to right side due to feedback loop (See Figure-01).

Clearly 0.777 V is close to GND (0 V) than V_DD (3.3 V). And so,

Constraints on Error amplifier ICMR

Our amplifier input common mode range should include 0.777 V which is close to GND.

Figure-04: ICMR of NMOS and PMOS input diff-amp

So to sense a common mode voltage near to GND, this time we could incline towards a PMOS.

But that contradicts with our output common mode constraint.

Possible modifications to Diff-amp

An NMOS input diff-amp can properly bias up the PMOS current source. But a PMOS input diff-amp can sense a near ground Common Mode voltage.

So the simplest modification we can do is to add level shifters. That is:

• Shift the input of NMOS input diff-amp upwards towards it's ICMR.
• Shift the output of PMOS input diff-amp upwards towards V_DD.

Figure-05: Diff-amps with appropriate level shifters

Figure-05 shows both possibilities. Both can be used as the feedback action will adjust the node voltages to settle to a steady state.

But, I am going to prefer NMOS variant for the following reasons:

1. NMOS Diff-amp produces \(V_{DD} - V_{SG}\) voltage by default with just common mode input. Very useful to directly bias the current source PMOS.

   What happens with a PMOS input Diff-amp?

   Had we used PMOS Diff-amp, there is a chance for some off-set to develop between the regulated nodes to push the output up to attain steady state. Think about it, Diff-amp operates using \(V_{out} = A_{D} * (V_{+} - V_{-})\). So to shift output upwards, you need to develop a non-zero difference between PLUS and MINUS terminals.

   Afterall, we can't set the output of this variant very close to a value unlike the NMOS input case.

2. Load of NMOS Diff-amp itself being a PMOS helps to improve matching with the current source PMOS.

3. Output is a high impedance, and can be easily compensated, by making it the dominant pole.

   What to do with PMOS input Diff-amp?

   You compensate by making the output of Diff-amp the dominant pole, and not the level shifted output. Level shifter presents low impedance at the output and would require large capacitors to compensate. Meanwhile, NMOS output itself is high-impedance node, and it is attached to gate terminals of Current source PMOS which is also high impedance and themselves presents some load, making it easy to compensate.

Bias-leg Design

Looking at Table-02, the V_GS and V_SG of NMOS and PMOS are 740 mV and 690 mV. And the supply is 3.3 V. So, we need to achieve a total voltage drop of 3.3 V using multiple V_GS or V_SG diode-connected drops (either 740 mV or 690 mV), depending on the MOSFET used and how many times it is utilized.

Let's do the math. We can see that if I used 2 NMOS and 2 PMOS in diode connected configuration as my bias leg, that adds up to:

\[\tag{2} V_{SUP,min} = 2 * V_{GS,n} + 2 * V_{SG,p} = 2 * (740m + 690m) = 2.86 V\]

That's almost amounts to supply of 3.3 V and clearly cannot accomodate anymore V_GS drops in it. The DC annotated schematic of such a bias leg is shown in Figure-06.

Figure-06: Two NMOS and two PMOS diode connected bias leg

Clearly, the increase in reference current is due to the excess supply voltage left from what we computed in Equation-02. We computed a minimum supply of 2.86 V and that leaves \(V_{excess} = V_{DD} - V_{DD,min} = 3.3 - 2.86 = 0.44 V\) which is distributed to all MOSFETs which results in increase of current.

Decreasing Minimum supply

We don't need to constrain ourselves to 2.86 V as that is the minimum supply needed for 10 µA. This is an error-amp, and we don't care about it's small signal parameter variation with bias current.

The supply can go even lower than 2.86 V by generating a current lesser than 10 µA. But, there is an absolute limit dictated by the threshold voltage, beneath which you will reach the subthreshold region. That's a no go. Biasing in the subthreshold will introduce horrible threshold mismatch, which will manifest as off-set at the input. We don't want that either.

With this in mind, let's compute the minimum supply which is barely enough to keep all MOSFETs ON. Looking at I/O Device — 500 nm table, we see that the threshold voltage of NMOS and PMOS are 560 mV and 510 mV.

\[\tag{3} V_{DD,min} = 2 * V_{TH,N} + 2 * V_{TH,P} = 2 * 0.56 + 2 * 0.51 = 2.14 V\]

Warning

This is an overestimate. Looking at Figure-06, both middle MOSFETs are suffering from body effect and their increase in threshold voltage is not accounted in Equation-03. It means, that the minimum limit will be slightly higher than 2.14 V.

We will see later that the actual limit is 2.63 V (See Figure-07 for DC annotated schematic at 2.63 V supply and Figure-09 for finding this limit) from simulations. But that is just 0.7 V below supply. Not even half the supply.

Figure-07: Four diode connected MOSFET at minimum possible supply

Notice that in Figure-07, both the middle MOSFETs are in sub-threshold (Region=3).

Now, we have two options:

• Accept 2.63 V as the minimum supply for error-amp and thus the reference.
• Decrease it even further by removing a V_GS drop.

Let's explore the second option, because I like to aim for a minimum supply close to V_DD/2.

Removing 1 V_GS drop

If we removed a V_GS (or 1 diode connected MOSFET) drop from Equation-02, we can go even lower than 2.63 V limit dictated by threshold voltage.

We can remove middle PMOS or middle NMOS, but, I am going to remove middle PMOS as the middle NMOS can be used as a cascode bias reference for current sink used in Diff-amp (Follow along, you will see this shortly).

\[\tag{4} V_{DD,min} = 2 * V_{TH,N} + V_{TH,P} = 2 * 0.56 + 0.51 = 1.63 V\]

Atleast now we can theoretically expect a minimum supply close to V_DD/2.

Figure-08: Two NMOS and one PMOS diode connected bias leg

The construction of such a bias leg is shown is Figure-08. The bias current generated is 31.5 µA for supply of 3.3 V.

Note

Notice that the length of bottom transistor is increased to four times by keeping four NMOS in series, and middle one is increased to two times similarly.

This is made to reduce the bias current generated. Had I used just the minimum length, the bias current would have increased, considering now it needs to split 3.3 V between just 3 MOSFETs.

Note

I did this roundabout way, because I got lazy in picking another size with longer length. Keeping MOSFETs in series to increase length is perfectly valid. [Ref. CMOS Circuit Design, Layout and Simulation, Fig 20.35]

Bias Leg Performance across supply

Sweeping the supply for Figure-06 and Figure-08 bias leg configurations over 2.5 V to 3.3 V yields Figure-09.

Figure-09: Performance of Bias Leg of Figure-06 and Figure-08 over supply

Clearly, four diode connected bias leg touches nA range (1 µA is the border to nA range) at 2.63 V while the three diode connected bias leg is still in µA range, i.e., all MOSFETs are still ON.

Current Sink from final bias leg (three diode connected)

Figure-10: Cascode Current Sink biased by bias Leg of Figure-08 Test bench

The performance of current sink (both simple and cascoded) seen Figure-11 shows that both cascode and simple current sink needs the same minimum voltage of 0.6 V.

Figure-11: Simple and Cascoded Current sink performance

With that being the case, there is absolutely no reason to avoid cascoded current sink.

Error Amp ICMR

Now we just need to see whether 0.777 V is in ICMR of our level shifted NMOS Diff-amp. Figure-12 shows the full schematic of error amp in ICMR measurement configuration and Figure-13 shows the simplified schematic of ICMR testbench.

Figure-12: Schematic diagram of Error Amplifier

Figure-13: Simplified schematic of ICMR Test bench

In order to justify the need of a level shifter, I have included the results of ICMR measurements for a simple NMOS diff-amp of Figure-03 (only the NMOS Input case) in Figure-14(a).

Figure-14: ICMR measurements for: (a) NMOS Diff-amp without level shifted inputs, (b) With level shifted inputs and (c) level shifted input variant at a supply of 2.5 V

Some observations on Figure-14:

1. Simple NMOS Diff-amp without level shifter has an ICMR of 1.6 V to 3.3 V (Figure-14(a)). Clearly doesn't include 0.777 V in it.
2. The level shifted variant has an ICMR of 0 V to 2.72 V. The upper limit is due to level shifter as it needs the gate voltage sufficiently lower to keep the level shifting PMOS ON (Figure-14(b)).
3. Figure-14(c) shows ICMR at a supply of 2.5 V (< 3.3 V). The ICMR is 0 V to 2.0 V roughly. Again limited by level shifter.

Success

The level shifted variant includes 0.777 V in it's ICMR.

To summarize:

VDD	ICMR
3.3 V	0 V to 2.7 V
2.5 V	0 V to 2.0 V

Table-03: ICMR summary for two cases of supply for Error-amp of Figure-12

Startup circuit design

Since the reasoning behind creating the startup circuit is thoroughly explained in the Startup Circuit Design section of BMR, I won't waste time and space to repeat it here.

Figure-15: Startup circuit schematic

However, I will provide commentary on Figure-15 to explain some choices in brief:

1. V_bias node is the Gate of Current sourcing PMOS (also the output node of error-amp). When the BGR has started up, the PMOS is biased to give 5 µA (as set by resistor, R₁. See Figure-17). V_bias receives appropriate voltage to set this current due to feedback loop.

2. When BGR has started up, you want to shut your leaker PMOS, and so, you need to pull it's Gate (or output of startup circuit) towards V_DD. This is achieved by keeping three 1/3 sized diode connected NMOS, which cannot sink 5 µA and hence push the output to supply.

   Note

   Keeping three diode connected NMOS in pull down shouldn't surprise you. Recall the discussion in Bias-leg Design, where we saw that many diode connected V_GS drops are needed to completely drop the supply of 3.3 V. That value for supply is huge, compared to what we get in core devices (L_min = 65 nm, V_DD = 1.2 V).

   So, it is very common to keep multiple diode connected MOSFETs in series especially in Long Channel design (or higher supply voltage designs).

   I would even say it is the recommended way to do this, than keeping 1 ridiculously long MOSFET to completely drop the supply to Ground.

3. The leaker PMOS is taken 1/1 because just by this ratio, it gave about 70 µA (See Figure-16, Right half), more than enough to pull the voltage of regulated node up to start the circuit.

   WARNING - Think of this 70 µA as a figure of merit for sizing this MOSFET and nothing more

   There is no DC path to conduct such a large current. See the discussion on Leaker NMOS Testbench in BMR to understand this statement. Especially the associated Warning at the end of that section for more info.

   In actual reality, it would leak few hundred nA at best. Nothing more.

Figure-16: Current leaked by a 1/1 PMOS

See the discussion on Leaker NMOS Testbench for more information regarding the testbench seen in Figure-16.

By now, our PTAT current generator design is finished, and Figure-17 shows the DC annotated Schematic.

Figure-17: DC Annotated schematic of PTAT current generator portion of BGR

Sometimes, even DC Op Point needs a startup circuit

If you ever see that your current generator doesn't bias up to it's operating point, try to replace your error-amp with an ideal VCVS of appropriate gain (say 10,000). Generally a VCVS biases up the current generator without the need of a startup.

But if even that fails, do add a startup circuit as it at least tries to induce a voltage to startup the circuit. It could be useful to troubleshoot the error.

Fixing PTAT Voltage Source resistor, R₂

The resistor value for R₂ is fixed by aiming for ZTC (Zero Temperature Co-efficient) operating point for output.

The output is made up of:

• CTAT Voltage source by bottom PNP Diode (8 in parallel).
• PTAT Voltage source by resistor R₂.

Looking at Figure-01, we can write,

\[V_{OUT} = V_{Q_3} + V_{R_2}\]

\[V_{OUT} = V_{Q_{3}} + L * \eta * V_T * \ln K\]

where, \(L = R_2/R_1\) and \(V_T\) is the thermal voltage.

Differentiating with respect to temperature and equating to zero (to find ZTC point) yields,

\[\frac{\delta V_{OUT}}{\delta T} = \frac{\delta V_{Q_3}}{\delta T} + L * \eta * \ln K * \frac{\delta V_{T}}{\delta T} = 0\]

Looking at Table-01, we get \(\delta V_{Q_3}/\delta T = -1.75~mV/C\), \(~\eta = 1003.6m~\) and \(~K = 8\). We also know \(\delta V_{T}/\delta T = 0.085~mV/C\). Plugging these values in above equation yields,

\[-1.75m + L * 1003.6m * \ln 8 * 0.085m = 0\]

\[L = 9.865\]

From L and R₁, we get,

\[R_2 = L * R_1 = 9.865 * 10.9k \approx 107.5k\]

Note

This value of R₂ is just a starting guess. That is, we will start our design with this value, and later adjust it to get better temperature performance in iterations.

DC Simulations

Since we hand calculated the value of R₂, we have to iterate to get better temperature performance. You will see what this means shortly.

Iteration 1

Let's summarise the parameters calculated for design till now:

Parameter	Value
R1	10.9 kΩ
R2	107.5 kΩ

Table-04: Values of Resistors R₁ and R₂ for iteration 1

The schematic diagram with the values in Table-04 is shown in Figure-18.

Figure-18: Series BGR schematic for iteration 1. Resistor values from Table-04

And the output voltage vs temperature can be seen in Figure-19.

Figure-19: BGR output performance across temperature for values of resistors in Table-04

Clearly, the output is showing PTAT nature instead of the characteristic bow.

Even though the output is more or less constant, i.e., around \(1.2695~V \pm 5~mV\), the temperature co-efficient is still not that good: 104.62 ppm/°C

Let's iterate.

Iteration 2

This is purely a trial and error process. But there is still some logic to it. Also, we will touch only the output PTAT voltage source resistor, R₂.

DO NOT TOUCH PTAT CURRENT GENERATOR RESISTOR, R₁

Do not touch R₁ as it sets the bias current in PTAT Current generator portion. Our calculations in Fixing PTAT Voltage Source resistor, R2 section depends on parameters for PNP Diodes listed in Table-01, which clearly characterized the PNP Diode for a bias current of 5 µA.

This bias current is set by value of R₁ and as such, changing this changes the bias current, and renders Table-01 as useless. DO NOT CHANGE THIS IN ANY ITERATION.

And if you do, regenerate Table-01 for your new operating point and recalculate an initial value for R₂ as PNP diodes now have different characteristics!

Before we change R₂, let's look at the kind of output we expect from BGR.

Figure-20: Characteristic bow in the output curve of a bandgap reference across temperature [Ref. Designing Analog Chips, Hans Camenzind, Fig. 7-6]

Comparing Figure-19 and Figure-20 we can see that the output curve is PTAT and is just the left portion of what we expect to get. So, we need to move towards the bow flat portion (maximum value point) by varying R₂.

To that end, try:

• Increasing R₂ by considerable amount (say 50 kΩ or even 100 kΩ), and re-simulate. See if you get the right portion of Figure-20, that is whether Figure-19 has changed to CTAT curve instead of PTAT curve.
  • If it did, we know that Bow characteristic lies between initial R₂ value of 107.5 kΩ and this new value, and so start to fine tune it in this range to get the desired curve.
  • If it still remained PTAT, then you adapt and do the opposite.
• Decreasing R₂ should be considered after you first try increasing it.

In this design, increasing had no effect and I adapted and started decreasing. For example, see Figure-21 which shows a CTAT like output instead of the PTAT one from Figure-19 for reducing R₂ value from 107.5 kΩ to 80 kΩ.

Figure-21: BGR output performance across temperature for reducing R₂ from 107.5 kΩ (Table-04 value) to 80 kΩ

From Figure-19 and Figure-21, we see that our correct value of R₂ to attain characteristic bow lies within 80 kΩ and 107.5 kΩ. That is:

\[80 ~k\Omega < R_2 < 107.5 ~k\Omega\]

CAUTION - Sometimes the characteristic bow can be inverted

Below, I have included an inverted bow which I got while designing the parallel realized BGR.

Figure-22: Inverted Bow output of parallel realized BGR (V_out = 0.61 V) (QUCS-S/NGSPICE)

I know Figure-22 seems unreal considering none of the textbooks cover an inverted bow as an output of BGR.

My point of showing this here, is to give an example where increasing R₂ (or decreasing) may result in an inverted bow as seen in Figure-22 and opposite to what is expected as shown in Figure-20.

Is the inverted bow correct? NO IDEA

I suspect that this is due to the type of resistor I used here, which is a High Resistivity Poly resistor. There are other variants available in 65 nm CMOS process like simple N+ and P+ poly, N-well resistors. But I chose the above one to save layout area.

See this Reddit post. It tries to find an answer for this. Maybe you can find a clue there.

With the preceeding discussion, I narrowed down value of R₂ to 99 kΩ.

Let's summarize the new values:

Parameter	Value
R1	10.9 kΩ
R2	99 kΩ

Table-05: Values of Resistors R₁ and R₂ for iteration 2

Changing R₂ in Figure-18 with the value in Table-05 (99 kΩ) yields:

Figure-23: BGR output performance across temperature for values of resistors in Table-05

Temperature performance seen in Figure-23 is leagues above what we saw in Figure-19 or Figure-21.

The output is about \(1.2227 \pm 475 \mu V\) with a temperature co-efficient of 19.416 ppm/°C.

Now that we got the characteristic bow, let's also see the supply dependance.

Supply Dependance

Sweeping the supply from GND to V_DD (3.3 V), yields Figure-24.

Figure-24: BGR output vs Supply

It seems that we can go as low as V_DD/2 (1.65 V) but the output is considerably lower than what's at V_DD (3.3 V). This is inevitable considering we really tried to aim for half the supply when designing the error-amp (See the discussion on Decreasing Minimum supply), but still, the output is only slightly less than 1.2 V.

I am not claiming V_DD/2 in our operating range, just, it is not bad.

TRANSIENT SIMULATION - Startup Action

Once again, the error-amp in feedback loop must be compensated as discussed in Using MOSFET as a capacitor to compensate the feedback loop. Please review that section as repeating it here will result in redundancy.

There, the discussion leaned towards PMOS as a capacitor due to current spikes. But in here, I don't care about the current but the voltage and so, I am going to lean towards an NMOS as a capacitor noting that the output of error-amp where we connect this, is at 2.67 V (See Figure-17).

And looking at I/O MOSFET as a capacitor table (repeated here in Table-06 for convenience), we can clearly see that:

• PMOS will behave poorly as a capacitor considering it needs a voltage less than 2.4 V whereas the voltage here is 2.67 V.
• NMOS will behave greatly as it is strongly inverted and more or less retains it's nominal value of 87.2 fF at all times.

Flavour	Drawn Size	Actual Size	VG	Nominal Capacitance
NMOS	8 / 8	4 µm / 4 µm	> 0.81 V	87.2 fF
PMOS	8 / 8	4 µm / 4 µm	< 2.40 V	82.7 fF

Table-06: MOSFET capacitance for specific sizes and Voltage conditions

Also, just to solidify this statement, Figure-25 shows C-V Curve of 8/8 I/O NMOS as a capacitor.

Figure-25: NMOS CV Curve for 8/8 size

And clearly NMOS attains it's nominal value and is guaranteed to retain it for this case.

And in this case, I am going to keep 5 such NMOS (each 8/8) in parallel to obtain a nominal capacitance of 435.9 fF (close to 450 fF).

The observant reader would have already spotted this capacitor in Figure-18.

Note

I found this 450 fF by just slapping an ideal capacitor of that value in place of NMOS capacitor and simulating a startup action. It's recommended to start with 500 fF and then possibly step up or step down in 100 fF or 50 fF steps while seeing startup action. I chose a suitable value in this way, and then constructed that value using NMOS/PMOS unit sizes characterized in MOSFET as Capacitor section of MOSFET Sizes & Parameter Summary page.

The startup action with this size NMOS as a capacitor is seen in Figure-26.

Figure-26: Startup transient with five 8/8 NMOS in parallel (Nominal Capictance of 435.9 fF)

To simulate the circuit turning ON case, supply starts to turn ON at 30 ns with a rise time of 10 ns to reach V_DD at 40 ns.

From Figure-26 the reference is stable and ON around the 80 ns mark.

Conclusion

Figure-27: Complete schematic of BGR

The design of BGR is complete. The parameters of series BGR are summarised in Table-07.

Parameter	Value	Comments
VREF	\(1.2227 \pm 475 \mu V\)	Generated output Voltage
TCBGR	19.416 ppm/°C	Temperature co-efficient of generated voltage
R1	10.9 kΩ	PTAT Current Generator resistor
R2	99 kΩ	PTAT Voltage Source resistor

Table-07: Series BGR Parameter summary

QUCS-S / NGSPICE simulations

This circuit is also built and tested in QUCS-S / NGSPICE and the simulation results are available in this document.