Analog IC Design Engineer (Fresher)

From Concept to Circuit
at 65 nm

Designing precision analog CMOS circuits — bandgap references, op-amps, and oscillators — simulated on Cadence Virtuoso & Spectre using a custom 65nm process node.

View Projects GitHub / QUCS-S Workspace
65 nm Custom CMOS Process
6 Analog Blocks Simulated
1.2 V Core Supply (VDD)
74.9 dB Op-Amp Gain · Short-Channel · 10kΩ‖10pF load
19.4 ppm/°C Best TC (BGR)
Work

Design Projects

↗
Feb 2026
Voltage Controlled Oscillator
Current-starved, 7-stage ring VCO. 500 MHz centre frequency, 172.8 Mrad/s/V tuning gain over 0.4–1.0 V control range.
f₀ = 500 MHz KVCO = 172.8 Mrad/s/V 1.2 V Core 65nm
↗
Jan 2026
Parallel Bandgap Reference
Parallel CTAT+PTAT current summation topology. 0.6 V output (~VDD/2), self-biased, 41.789 ppm/°C temperature coefficient.
VREF = 0.6 V 41.789 ppm/°C 1.2 V supply Core 65nm
↗
Dec 2025
Series Bandgap Reference
Series CTAT+PTAT voltage summation. 1.22 V silicon bandgap output, self-biased, 19.416 ppm/°C on I/O 500nm MOSFET.
VREF = 1.22 V 19.416 ppm/°C 3.3 V supply I/O 500nm
↗
Oct 2025
Rail-to-Rail Op-Amp
Folded cascode, parallel NMOS+PMOS input stages, Class AB output. Characterised across all three CMR regions under 10 kΩ ‖ 10 pF load.
Gain 67.1–74.9 dB UGB 47.5–96.9 MHz PM 54°–75° Core 65nm
↗
Sep 2025
General Bias Circuit
Derives wide swing cascode current source and sink bias voltages plus Class AB output stage bias from BMR. Supply-independent biasing for all analog blocks.
Wide swing cascode bias Class AB Bias IBIAS = 10 µA VDD,min = 0.7 V 1.2 V Core 65nm
↗
Sep 2025
Beta Multiplier Reference
Resistor-based, self-biased supply-independent current reference. Generates 10 µA bias current for all subsequent analog blocks.
IBIAS = 10 µA VDD,min = 0.7 V Supply Independent 1.2 V Core 65nm
Background

Skills & Education

EDA Tools
  • Cadence Virtuoso
  • Spectre
  • QUCS-S
  • NGSpice
Designed Analog Blocks
  • Bandgap References
  • Bias Circuits (BMR)
  • Rail-to-Rail Op-Amp
  • Ring Oscillator / VCO
  • Comparators
Process Experience
  • 65nm Custom CMOS
  • 90nm GPDK
  • 180nm Custom CMOS
Education
  • 2024 – 2025
    M.Tech — VLSI Systems Design
    Redacted  ·  redacted, India  ·  Not completed
  • 2019 – 2023
    B.Tech — Electronics & Communication Engineering
    Redacted  ·  redacted, India
Credentials

Certifications

NPTEL — IIT
Analog IC Design
Jan – Apr 2023
NPTEL — IIT
Circuit Analysis for Analog Designers
Jan – Apr 2023