Disclaimer

All circuits documented here are simulation-only designs — no physical fabrication or silicon verification has been performed. Results are based on Cadence Spectre and NGSpice simulations using real foundry BSIM4 PTM 65nm models.

These documents are shared for portfolio and demonstration purposes only and are not intended as educational or reference material. Use in any production or critical application without independent verification is strongly discouraged.

The documentation is Licensed under CC BY 4.0, while the QUCS-S Schematics are Licensed under MIT License. Read the LICENSE.txt in each of these repositories for more information.

MOSFET Sizes & Parameter Summary¶

This page serves as the central device reference for all designs documented on this site. Unless mentioned explicitily, all circuits reference back to this page for transistor sizing and small-signal parameters.

How to read these tables

Drawn dimensions are in units of minimum feature size. For core 65nm devices, multiply by 65 nm to get actual dimensions. For example, W/L = 43.1 / 2 means W = 43.1 × 65 nm = 2.8 µm, L = 2 × 65 nm = 130 nm.
All identifiers follow standard analog IC design notation — subscripts are used throughout.
NMOS and PMOS parameters are shown side by side for direct comparison.

Analog Models¶

Core Device — 65 nm¶

Process: Custom 65nm CMOS · Supply: V_DD = 1.2 V · L_min = 65 nm

Regular Threshold Voltage (RVT)¶

Parameter	NMOS	PMOS	Comments
I_D	10 µA	10 µA	Approximate, depends on operating point
W/L (Drawn)	43.1 / 2	121.5 / 2	Selected based on I_D and V_ov
W/L (Actual)	2.8 µm / 130 nm	7.9 µm / 130 nm	Absolute dimensions
V_DSsat	60 mV	60 mV	From R_out vs V_DS curve
V_ov	70 mV	70 mV	5% of VDD is recommended for general design. Chosen slightly greater than that.
V_TH	430 mV	400 mV	From g_m curve of a 50/2 device (V_DS = 100 mV)
V_GS	500 mV	470 mV	With no body effect
V_sat	126.5 * 10³ m/s	124.4 * 10³ m/s	Carrier saturation velocity, From BSIM4 model
t_ox	26 Å	27.5 Å	Oxide thickness, From BSIM4 model
C'_ox	13.3 fF/µm²	12.6 fF/µm²	ε_ox = ε_{r_SiO2} * ε₀ (ε_{r_SiO2} = 3.9 & ε₀ = 8.85 * 10^-12)
C_ox	4.84 fF	12.94 fF	C_ox = C'_ox * W * L (W,L - Actual dimensions)
C_gs	3.23 fF	8.63 fF	C_gs = ⅔ * C_ox
C_gd	0.168 fF	0.206 fF	C_gd = CGDO * W (CGDO_n = 59.9 pF/m & CGDO_p = 26.1 pF/m), CGDO from BSIM4
g_m	115.83 µA/V	130.51 µA/V	At VDS = 0.1 V
r_out	214.89 kΩ	221.02 kΩ	At I_D = 10 uA
g_ds	4.65 µA/V	4.52 µA/V	1/r_out
A_v-open	24.89 V/V	28.84 V/V	g_m * r_out, Open Circuit Gain
λ	0.46 V⁻¹	0.45 V⁻¹	L = 2
f_T	5.5 GHz	2.75 GHz	Approx at L = 2

Low Threshold Voltage (LVT)¶

Parameter	NMOS	PMOS	Comments
I_D	10 µA	10 µA	Approximate, depends on operating point
W/L (Drawn)	38.5 / 2	93.8 / 2	Selected based on I_D and V_ov
W/L (Actual)	2.5 µm / 130 nm	6.1 µm / 130 nm	Absolute dimensions
V_DSsat	50 mV	60 mV	From R_out vs V_DS curve
V_ov	70 mV	70 mV	5% of VDD is recommended for general design. Chosen slightly greater than that.
V_TH	350 mV	350 mV	From g_m curve of a 50/2 device (V_DS = 100 mV)
V_GS	420 mV	420 mV	With no body effect
V_sat	133 * 10³ m/s	75.5 * 10³ m/s	Carrier saturation velocity, From BSIM4 model
t_ox	26 Å	27.5 Å	Oxide thickness, From BSIM4 model
C'_ox	13.3 fF/µm²	12.6 fF/µm²	ε_ox = ε_{r_SiO2} * ε₀ (ε_{r_SiO2} = 3.9 & ε₀ = 8.85 * 10^-12)
C_ox	4.32 fF	9.99 fF	C_ox = C'_ox * W * L (W,L - Actual dimensions)
C_gs	2.88 fF	6.65 fF	C_gs = ⅔ * C_ox
C_gd	0.204 fF	0.104 fF	C_gd = CGDO * W (CGDO_n = 81.5 pF/m & CGDO_p = 17.0 pF/m), CGDO from BSIM4
g_m	121.41 µA/V	116.21 µA/V	At VDS = 0.1 V
r_out	130.25 kΩ	118.14 kΩ	At I_D = 10 uA
g_ds	7.68 µA/V	8.46 µA/V	1/r_out
A_v-open	15.81 V/V	13.73 V/V	g_m * r_out, Open Circuit Gain
λ	0.77 V⁻¹	0.85 V⁻¹	L = 2
f_T	6.3 GHz	3.0 GHz	Approx at L = 2

I/O Device — 500 nm¶

Process: Custom 65nm CMOS · Supply: V_DD = 3.3 V · L_min = 500 nm

Note

I/O devices are used exclusively in large-signal designs (Bandgap References). Only large-signal parameters are characterized here — small-signal parameters are not tabulated.

Parameter	NMOS	PMOS	Comments
I_D	10 µA	10 µA	Approximate, depends on operating point
W/L (Drawn)	5.8 / 1	13.8 / 1	Selected based on I_D and V_ov
W/L (Actual)	2.9 µm / 500 nm	6.9 µm / 500 nm	Absolute dimensions
V_DSsat	250 mV	200 mV	From R_out vs V_DS curve
V_TH	560 mV	510 mV	From g_m curve of a 20/1 device (V_DS = 180 mV)
V_GS	740 mV	690 mV	With no body effect

Digital Models¶

Core Device — 65 nm¶

Process: Custom 65nm CMOS · Supply: V_DD = 1.2 V · L_min = 65 nm

Switching Parameters (General)¶

Switching resistance per unit width and oxide capacitance per unit area. For sizing.

R_n (W Drawn)	R_p (W Drawn)	Scale Factor	C_oxn (W, L Actual)	C_oxp (W, L Actual)
33.846 kΩ/W	67.692 kΩ/W	65 nm	13.3 fF/µm² × W × L	12.6 fF/µm² × W × L

How to use these values

W in the resistance columns is the drawn width in units of L_min. W and L in the capacitance columns are actual dimensions in µm. For example, for an NMOS with W/L (Drawn) = 10/1: R_n = 33.846k / 10 = 3.4 kΩ, and C_oxn = 13.3 fF/µm² × 0.65 µm × 0.065 µm = 561 aF.

Switching Parameters (Chosen Size)¶

Flavour	W/L (Drawn)	W/L (Actual)	R_n,p	C_oxn,p
NMOS	10/1	650 nm / 65 nm	3.4 kΩ	561 aF
PMOS	20/1	1.3 µm / 65 nm	3.4 kΩ	1.06 fF

MOSFET as Capacitor¶

Note

The control voltage applied at the gate of MOSFET (both NMOS and PMOS) is always referenced to GND as shown in Figure-01

MOSFET Capacitor Configuration — **Figure-01:** MOSFET as a capacitor to VDD and GND

Core Device — 65 nm¶

Process: Custom 65nm CMOS · Supply: V_DD = 1.2 V · L_min = 65 nm

Flavour	Drawn Size	Actual Size	V_G	Nominal Capacitance
NMOS-RVT	10 / 10	650 nm / 650 nm	> 0.6 V	5.2 fF
NMOS-RVT	20 / 20	1.3 µm / 1.3 µm	> 0.6 V	20.9 fF
PMOS-RVT	10 / 10	650 nm / 650 nm	< 0.6 V	5.2 fF
PMOS-RVT	20 / 20	1.3 µm / 1.3 µm	< 0.6 V	20.4 fF

I/O Device — 500 nm¶

Process: Custom 65nm CMOS · Supply: V_DD = 3.3 V · L_min = 500 nm

Flavour	Drawn Size	Actual Size	V_G	Nominal Capacitance
NMOS	8 / 8	4 µm / 4 µm	> 0.81 V	87.2 fF
PMOS	8 / 8	4 µm / 4 µm	< 2.40 V	82.7 fF